IEC 60749-41-2020 SEMICONDUCTOR DEVICES – MECHANICAL AND CLIMATIC TEST METHODS – Part 41 : Standard reliability testing methods of non-volatile memory devices

IEC 60749-41-2020 SEMICONDUCTOR DEVICES – MECHANICAL AND CLIMATIC TEST METHODS – Part 41 : Standard reliability testing methods of non-volatile memory devices. 3.4 data pattern mix of several 1 s and 0s in the memory and their physical or logical positions Note 1 to entry: A device can be single-bit-per-cell (SBC), meaning that one physical memory cell stores a “0” or a “1 “, or multiple-bits-per-cell (MBC), meaning that one cell stores typically two bits of data: “00”, “01 “, “1 0”, or “1 1 “. In some MBC memories, the two bits represent logically-adjacent bit-pairs in each byte of data. For example, for 2 bits per cell, a byte containing binary data 1 01 1 0001 would correspond to four physical cells with data 2301 in base-four logic. In other MBC memories, the two bits can represent bits in entirely different address locations. For an SBC memory a physical checkerboard pattern consists of alternating 0s and 1 s, with each 0 surrounded by 1 s on either side and above and below; a logical checkerboard pattern consists of data bytes AAH or 55H in which each 0 is logically adjacent to 1 s. In some qualifications only logical positions are known. 3.5 endurance ability of a reprogrammable read-only memory to withstand data rewrites and still comply with applicable specifications Note 1 to entry: EEPROM device specifications often require an erase step before reprogramming data; in this case a data rewrite includes both erase and programming steps, which together are called a program/erase cycle. Direct-write memories allow data to be written directly over old, without an erase; in this case the use of the generic term “program/erase cycle” will refer to a single rewrite with no erase. For single-bit-per-cell (SBC) memories that require an erase step, one program/erase cycle consists of programming cells (typically to “0”) and then erasing (“1 “). For the comparable multiple-bits-per-cell (MBC) case, a cycle would consist of programming cells (to “0”, “1 “, or “2” for two bits per cell) and then erasing (“3” for two bits per cell). Note 2 to entry: Endurance cycling consists of performing multiple rewrites in succession, and the data pattern or patterns for these rewrites must be chosen. There is no one data pattern or set of patterns that is worst-case for all failure mechanisms. For example, for floating-gate memories a fully programmed pattern is worst-case for charge transfer,...